1. Field of the Invention
The present invention relates generally to a buffering data storage device, and more particularly, to a configuration of a first-in first-out (FIFO) type data storage device interposed in a data transmission path and having a number of storage stages which are changed according to the data transfer situation in the output portion thereof.
2. Description of the Background Art
If and when data transmission is made between asynchronous systems, a buffer for regulating data transfer is generally provided between the processors in each of the systems. A first-in first-out (FIFO) memory for outputting received data according to the input order is generally used as such a buffer.
In FIG. 1, when data transfer is made from a processor A to a processor B, which processors are asynchronously operated, an FIFO memory 3 is provided between the processor A and the processor B. This FIFO memory 3 stores data applied from the processor A in the received order, to output the stored data in the same order as the input order in response to a read-out designating signal from the processor B. In addition, the FIFO memory 3 monitors the storing state therein, to apply a data transfer inhibiting signal to the processor A when the storing state therein becomes full.
Since this FIFO memory 3 need not receive an address indicating a data storage location from the processors A and B, the interface with a processor (or a system) becomes simple. Thus, the FIFO memory 3 is widely used as a buffer for transferring data between systems which are asynchronously operated or between processors having different speeds of data processing.
The time required for a data processor to process data differs depending on the content of applied data and the content of processing required in the processor. Thus, in an asynchronous system, a group of resultant data packets processed in each of the processors A and B is not always transmitted at the same time interval. As a result, the amount of data stored in the FIFO memory 3 is not fixed, and a group of data transmitted from the processor A stays in the FIFO memory 3 due to the difference in processing time in the processor B. In order to decrease such a stay to the utmost, a data transfer control signal must be received and sent between each of the processors A and B and the FIFO memory 3, so which increases the amount of hardware in the processor.
Additionally, if and when the FIFO memory 3 is includes, for example, a multi-stage shift register, the number of storage stages does not vary during the operation, so that respective times required for transferring one data are the same irrespective of the amount of data to be transferred. Thus, in this case, if only one word data (one packet data) exists, for example, there is delay in the data transfer, corresponding to the number of storage stages in the FIFO memory. As a result, data transmission is not made at high speed.